Industry verticals
Warm Introductions in Semiconductor and Electronics Sales
Semiconductor tool and IP procurement operates on 18-to-36-month design-win cycles where vendor selection happens once at design-start and switching mid-design is prohibitively costly. The introduction that matters is not to procurement but to the IC design architect or principal engineer, before the design cycle begins: through a reference design-win customer who has taped out silicon with your technology, a foundry qualification that puts your product on the OIP partner list, or a peer relationship built through IEEE technical society participation.
Why semiconductor technology procurement is a design-win problem before it is a sales problem
EDA tools, semiconductor IP blocks, process design kits, and specialty components used in chip design are not purchased in the way that enterprise software or industrial equipment is purchased. The decision is made once, at design-start, by a principal IC design engineer or chip architect who selects the tool or IP that will be integrated into a design that may run for 18 to 36 months before producing revenue. Once a tool or IP block is embedded in an active design, with simulation data accumulated, verification procedures built around it, and engineering time invested in its integration, switching is essentially impossible short of a critical failure. Cold outreach to an IC design team therefore lands in a market where the relevant decision has either already been made for the current design or has not yet been triggered for the next one.
The vendors who win design-win share in the semiconductor market do it through three structural paths: reference design-win customers who have already taped out silicon using the technology and can speak to its integration behavior from production experience, foundry qualification programs that place the technology on the partner registry every design team consults when setting up a new design on a specific node, and IEEE technical society participation that builds peer credibility with the design engineers who make the selection decisions. Each path works because it solves the trust problem that the design-win market creates: the prospect needs to know, before committing 18 to 36 months of engineering effort, that the technology will perform as claimed. The only evidence that persuades a senior IC design engineer is evidence from someone who has already run the technical risk.
1. The reference design-win customer as the peer connector
Semiconductor technology procurement is fundamentally a design-win market: the meaningful commercial relationship is not an ongoing service contract or a renewable subscription but a decision, made once at design-start, to use a particular EDA tool, IP block, process design kit (PDK), or component in a chip that will go into production. Once a design team has committed to a tool or IP block for a design, switching mid-design is prohibitively costly: the team’s invested engineering time, the tool’s integration with their existing flow, and the simulation and verification outputs that depend on it all become switching barriers that compound as the design matures. This switching-cost structure means that the introduction to a new chip design team must happen before design-start, when the team is evaluating tools and IP for the next design cycle. And the most credible introduction at that stage comes not from a vendor sales team but from a peer design engineer at another company who has already committed the same tool or IP through a complete design cycle and taped out working silicon. That engineer can speak to integration complexity, foundry compatibility, verification sign-off behavior, and the post-silicon correlation between simulation and real chip performance, none of which a vendor can certify with the same credibility as someone who has run the complete engineering risk. The Granovetter bridge-position logic applies directly: the reference design-win customer sits between the vendor and the prospective new design team with information and credibility that neither party can access across the gap without that bridge.
How to use this in practice
Identify your existing design-win customers who have successfully taped out on the foundry nodes and process technologies your target prospects are using or planning to use. The introduction is most credible when the reference customer is engineering-peer equivalent to the prospect: a small fabless AI chip company’s principal IC design engineer is a more compelling reference for a similar prospect than a large established IDM’s design team, because the engineering constraints and risk profile are more directly comparable. Build the mechanism: run a structured reference program where satisfied customers are specifically asked whether they would be willing to discuss their experience with other non-competing design teams, and provide them with a brief technical framing document that articulates what the conversation should cover (integration steps, verification sign-off process, performance correlation) so the reference conversation is genuinely useful to the prospective design team rather than a generic testimonial. The primary venue for reference customer introductions is ISSCC, DAC, and DATE, conference environments where principal engineers from different companies are in professional-peer mode and where a direct introduction between a reference customer and a prospect carries the full weight of the shared conference context.
2. Foundry qualification as the trust credential and propagation engine
The foundry qualification process (the months-long technical characterization, silicon validation, and process integration work required to certify that a technology is compatible with a specific foundry node) functions simultaneously as a trust credential and as an automatic introduction mechanism to every design team starting a design on that node. TSMC’s Open Innovation Platform (OIP) lists qualified IP and EDA tool partners for each process node, and a design team starting work on TSMC’s N3E, N2, or A16 node will consult the OIP as a first step in identifying which EDA tools, IP blocks, memory compilers, standard cell libraries, and interface IP are qualified and validated for that process. Intel Foundry’s Accelerated Design Enablement (ADE) program and Samsung Foundry’s Foundry Partner Program operate the same qualification-and-introduction structure. The foundry qualification is precisely the Schmitt and Van den Bulte trust-transfer mechanism applied at institutional scale: the foundry’s own engineering team has characterized the vendor’s technology against process specifications, run silicon validation, and certified compatibility, a process that involves the foundry staking its own engineering credibility and process yield reputation on the result. When a design team at a fabless company evaluates EDA tools or IP for a new design on a qualified node, a vendor whose technology is on the OIP partner list arrives with the foundry’s implicit endorsement substituting for the independent technical evaluation that the design team would otherwise need to conduct. The practical propagation effect is significant: a technology that achieves TSMC N3 qualification reaches every fabless design team globally that is starting a design on N3, a simultaneous introduction to hundreds of potential design-win customers that no direct outreach can replicate in scope or credibility.
How to use this in practice
Prioritize foundry qualification for the process nodes where your target design-win customers are building their next-generation designs. For EDA tools, this means working with the foundry’s technology partnerships team to achieve OIP qualification: a process that requires providing the foundry with PDK-integrated tool flows, running test chips, and meeting the foundry’s interoperability specifications. For IP vendors, TSMC IP Partner Program, Intel Foundry IP Alliance, and Samsung Foundry IP Ecosystem each have a structured qualification process with specific silicon validation requirements. Track where qualified IP in your category is being designed in: the DAC IP track and TSMC OIP Technology Symposium are venues where foundry qualification status and design-in momentum are publicly discussed among design engineers. Invest in the qualification for nodes where design activity is concentrating: N3 and N2 for leading-edge logic, N6 and N7 for cost-sensitive AI and networking designs, and specialty nodes (BCD, FDSOI, 130nm RF) for analog and mixed-signal markets where foundry relationships with design teams are more durable than in the highly competitive logic market.
3. IEEE technical society participation as engineering peer introduction infrastructure
The IEEE Solid-State Circuits Society (SSCS), the IEEE Electron Devices Society (EDS), and the Design Automation Conference (DAC) create the professional communities where the chip architects, principal IC design engineers, and technical directors who control tool and IP selection at design-start spend time and build peer relationships outside of program pressure. ISSCC (the International Solid-State Circuits Conference, co-organized by the IEEE SSCS) is the most prestigious venue in integrated circuit design: a principal engineer’s paper accepted at ISSCC demonstrates the technical capability to design and verify silicon that meets the conference’s peer-review standard, and that demonstrated capability is the specific signal that other design engineers use to assess whether a vendor’s engineering team understands the real problems in IC design. A company whose technical staff present silicon results at ISSCC (measurement data from fabricated chips, not simulation) builds the peer credibility in the IC design community that generates introductions organically: the design engineer who heard the ISSCC presentation has a specific technical reference point for a follow-up conversation in a way that a cold pitch does not provide. DAC, the Design Automation Conference, serves the EDA tool and design automation community: program committee participation, technical paper presentations, and working-group involvement in topics like formal verification, physical design, or DFT (design for test) build the peer relationships with the design engineering managers and tool evaluation leads who will make EDA tool selection decisions at their design teams. Granovetter’s weak-tie mechanism is the structural explanation for why these technical conference relationships generate commercial introductions: the design engineer who knows a vendor’s technical staff from shared committee work or a hallway conversation at ISSCC is a structurally different contact from a prospect receiving cold outreach. The weak-tie bridge between the vendor’s community and the prospect’s community carries information and credibility that the dense cluster of the prospect’s existing vendor relationships does not.
How to use this in practice
Identify which IEEE technical societies and conferences are most directly relevant to your specific technology category. For analog and mixed-signal IP vendors, IEEE SSCS and ISSCC are the primary community; for digital IP and SoC design, the Design Automation Conference and IEEE International Symposium on Circuits and Systems (ISCAS) are the relevant venues; for semiconductor process equipment and materials, the ECS (Electrochemical Society) and the MRS (Materials Research Society) concentrate the process engineers and materials scientists who make qualification decisions. Invest in technical community participation that requires actual engineering contribution (paper submission, working group membership, program committee review) rather than exhibition booth presence. The credibility signal that generates peer introductions is demonstrated technical depth, not visibility, and the IC design community is experienced at distinguishing vendors who are technically substantive from those who are commercially present at conferences. A company whose lead design engineer has three ISSCC-accepted papers and serves on the DAC technical program committee is positioned for engineering-peer introductions in a way that a company with only a trade show booth presence is not.
Why the semiconductor design team is hard to reach through conventional means
Design-win cycles run 18 to 36 months: the introduction window is design-start
Semiconductor procurement timelines are measured in design cycles, not procurement quarters. A fabless company starting a new chip design will select EDA tools, IP blocks, and key interface IP at design-start, typically 18 to 36 months before the chip reaches production volume. Once tools and IP are integrated into the design flow and the design team has built workflows around them, switching is prohibitively costly: the sunk engineering cost in the existing flow, the simulation data accumulated using the current tool, and the verification sign-off procedures built around the specific IP implementation all compound to make mid-design switching essentially impossible except in response to a critical failure. The commercial implication is that a warm introduction that does not arrive before design-start misses the design-win opportunity entirely, regardless of the vendor’s technical quality. Vendor relationships that generate design-win introductions are built in the 6 to 12 months before a design team’s design-start, through reference customer peer conversations, foundry OIP qualification, and conference relationships, not during the design cycle itself.
The decision-maker is the IC design architect or principal engineer, not procurement
Semiconductor tool and IP selection is a technical decision made by senior engineering staff: the chip architect who defines the design methodology, the principal IC design engineer who owns the implementation flow, or the design manager who allocates engineering resources to tool evaluation. Procurement staff execute purchase orders for approved tools and IP; they do not evaluate technical alternatives or control vendor selection in the way that procurement functions in other industries do. A warm introduction routed through a purchasing contact does not reach the person who makes the technical selection decision. The effective introduction target is the engineering organization: the chip architect who sets the tool and methodology strategy, the physical design lead who evaluates EDA physical implementation tools, or the IP integration team lead who assesses IP quality and integration support. These engineering decision-makers build their views on tool and IP quality primarily through peer conversations with engineers at other companies and through technical community participation, not through vendor-initiated outreach or evaluation cycles that procurement manages.
Foundry node transitions create structured windows for new vendor consideration
When the semiconductor industry transitions to a new process node (as it has through 7nm, 5nm, 3nm, and now 2nm and beyond at TSMC, Intel Foundry, and Samsung Foundry), design teams that are moving to the new node need to re-evaluate their tool and IP stack for node compatibility. The PDK for a new node has different device models, different layout rules, and different parasitic extraction models than the prior node, and tools and IP that were validated for the previous node may require updated versions, re-characterization, or replacement for the new node. This node transition dynamic creates a structured re-evaluation window, often 12 to 18 months before the first commercial designs on the new node, during which a vendor whose technology is qualified and validated for the new node has a genuine evaluation opportunity with design teams that are adopting the node for the first time. A vendor who has achieved OIP qualification for TSMC N3 has a warm introduction opportunity with every design team that is considering N3 for their next design, specifically because the foundry qualification represents the technical validation that the design team would otherwise have to conduct themselves.
Common questions
Why is cold outreach to IC design teams almost entirely ineffective in semiconductor B2B sales?
Several structural factors compound each other. IC design teams are small and technically intense: a 50-person fabless chip company may have 30 to 40 engineers focused entirely on design and verification, with very limited capacity for unsolicited vendor evaluation. Tool and IP evaluation requires substantial engineering time: setting up a tool evaluation, running test cases through a real design flow, and comparing results against existing tools is a weeks-long process that a design team can only undertake for a small number of candidates. The technical gatekeeping structure means that a cold pitch to a design team that has not already been qualified through a peer introduction, foundry reference, or conference relationship starts at a significant credibility deficit: the design team has no signal about the vendor’s engineering quality, post-sales support capability, or PDK compatibility beyond what the vendor itself claims. The warm introduction (through a reference design-win customer who has run the tool through a complete design cycle, a foundry OIP qualification that validates node compatibility, or a peer relationship built through ISSCC or DAC) solves the credibility problem before the evaluation even begins.
What is the TSMC Open Innovation Platform (OIP) and how does it function as an introduction mechanism?
TSMC’s Open Innovation Platform is a qualification and partner registry that lists EDA tools, IP, and design infrastructure components that have been validated and certified for specific TSMC process nodes. When a fabless design team at any company starts a new design on TSMC N3E or N2, consulting the OIP is a standard step in their design setup process: it identifies which tools are certified to work with the TSMC PDK for that node, which IP blocks have been silicon-validated, and which ecosystem partners have completed TSMC’s interoperability testing. A vendor whose technology appears on the OIP partner list for a specific node has effectively received a simultaneous introduction to every design team globally that is adopting that node, because those design teams will encounter the vendor’s name and qualification status as part of their standard design setup workflow, rather than as an unsolicited vendor pitch. Intel Foundry’s Accelerated Design Enablement (ADE) program and Samsung Foundry’s Foundry Partner Program operate the same structure: qualification on the foundry’s ecosystem program is both a technical validation and a propagation mechanism that reaches every design team starting a design on the qualified node.
How does EDA tool sales differ from semiconductor IP licensing in terms of introduction mechanics?
The introduction mechanics share the same three structural paths (reference design-win customer, foundry qualification, IEEE technical community), but the details differ by product type. For EDA tools, foundry PDK qualification is the most powerful single introduction mechanism because design teams will not use an EDA tool that is not validated for their foundry and node. The OIP partner list is effectively a whitelist for EDA tool consideration. For semiconductor IP (hard macros, soft IP blocks, interface IP, memory compilers), the reference design-win customer conversation is particularly valuable because IP integration complexity (clock domain crossings, interface protocol compatibility, foundry-specific cell library alignment) is something that a reference customer with production silicon experience can speak to in ways the vendor cannot substitute. IP licensing also involves architectural fit (whether the IP block fits the specific design’s power, performance, and area targets), and peer engineers who have used the IP in similar applications can give direct, credible assessments of that fit. For MEMS, analog, and mixed-signal components sold as physical devices rather than licensed designs, the reference customer conversation is also the primary mechanism, supplemented by IEEE SSCS and ISCAS relationships with analog design engineers who make the component specification decisions.
What is ISSCC and why does a paper acceptance there matter for semiconductor B2B relationships?
ISSCC, the International Solid-State Circuits Conference, is the most prestigious peer-reviewed venue in integrated circuit design. A technical paper accepted at ISSCC must present novel silicon results: measured data from a fabricated chip demonstrating the claimed performance, not simulated projections. The review committee, composed of senior IC design engineers from leading companies and universities globally, assesses whether the work represents a genuine advance in solid-state circuits design. A company whose principal engineer has a paper accepted at ISSCC has demonstrated, through a rigorous peer-review process involving the same design engineers who will be evaluating vendor tools and IP, that the company’s technical staff can design and verify silicon at world-class performance levels. That demonstrated capability is the most direct credibility signal available in the IC design community, because it is grounded in silicon evidence reviewed by the exact technical peers whose opinion of a vendor’s engineering quality will determine whether they take an evaluation seriously. Conference peer relationships formed at ISSCC (in hallway conversations, poster sessions, and the technical workshops that accompany the conference) generate the warm introductions that translate into design-win evaluations, because the design engineer knows the vendor’s technical staff by name and by work.
How do design-win dynamics differ for fabless companies versus IDMs (Integrated Device Manufacturers)?
Fabless companies (chip designers that do not own manufacturing facilities and outsource production entirely to foundries) are the primary growth market for EDA tools and semiconductor IP, and their design-win economics are the most direct: every design-start is a potential new win, and the design team evaluates tools and IP independently for each new chip program. IDMs, vertically integrated companies like Intel, Samsung Semiconductor, and Texas Instruments that both design chips and operate their own fabs, have more complex procurement structures where tool and methodology decisions are often made at the division level or corporate EDA infrastructure level, with individual design teams working within a pre-approved tool infrastructure. The warm introduction mechanism differs accordingly: at fabless companies, the relevant introduction target is the chip architect and principal engineer at the design team level; at IDMs, the EDA infrastructure team and methodology group that manages tool approval for the division or business unit is the introduction target for initial tool qualification, while individual program teams are relevant for new IP evaluation. Reference design-win customers at comparable fabless companies are the strongest introduction signal for other fabless design teams; for IDMs, division-level methodology leads and the internal champions who drove prior tool adoption carry the most credible endorsement.
Are there introduction mechanics specific to advanced packaging and chiplet ecosystem sales?
Advanced packaging (heterogeneous integration through technologies like TSMC CoWoS, Intel EMIB/Foveros, Samsung X-Cube, and ASE/Amkor packaging platforms) and chiplet ecosystem development introduce a new category of warm introduction mechanics beyond the traditional IC design-win path. The UCIe (Universal Chiplet Interconnect Express) consortium and the Open Compute Project chiplet working groups concentrate the architects from hyperscalers, AI chip companies, networking semiconductor vendors, and foundry/OSAT partners who are defining the chiplet interoperability standards that will govern multi-die package procurement for the next decade. Participation in UCIe working groups, where Intel, AMD, Arm, Qualcomm, TSMC, Samsung, and the major hyperscalers collaborate on die-to-die interface standards, builds the peer relationships with the architects who will specify chiplet interface IP, packaging EDA flows, and multi-die verification tools for the leading advanced packaging programs. The packaging OSAT (Outsourced Semiconductor Assembly and Test) companies (ASE Technology Group, Amkor, JCET Group) function as portfolio connectors in advanced packaging analogous to the foundry qualification mechanism in front-end design: a packaging technology or material that an OSAT has qualified for their advanced packaging process reaches every chip company that uses that OSAT for CoWoS, fan-out wafer-level packaging, or 2.5D/3D integration.
Sources and context: IC Insights (now TechInsights) on semiconductor design-win cycles and vendor qualification timelines; SEMI EDA Industry Statistics on design tool adoption patterns; TSMC Open Innovation Platform (OIP) documentation on node qualification and ecosystem partner certification; ISSCC general chair reports on conference scope and attendance; DAC technical program committee composition; Granovetter (1973) on bridge positions applied to reference design-win customer as peer connector between vendor and prospective design team; Doney and Cannon (1997) on trust mechanisms in industrial procurement applied to long-cycle IC design tool and IP selection; Schmitt and Van den Bulte (1996) trust-transfer mechanism applied to foundry qualification as institutional endorsement substituting for independent technical evaluation by each design team.